Micron's HBM Roadmap Raises Both Capacity and Cost Stakes

Micron's next generations of artificial-intelligence memory could require more manufacturing capacity for each bit they produce, a constraint that may support pricing but also raises the cost and complexity of expanding supply.

During Micron's October 21 technology webinar, President and Chief Technology and Products Officer Scott DeBoer said the company's roadmap moves toward products that consume progressively more wafers per bit than standard DRAM. High-bandwidth memory, or HBM, stacks multiple memory dies and connects them vertically. More advanced vertical designs add interconnections and processing steps, which can reduce the number of usable chips produced from a wafer.

Micron's own HBM4 manufacturing description illustrates the challenge. The process begins with three kinds of wafers: DRAM dies with through-silicon vias, a thicker top die and a logic die. Only tested dies move to assembly, where multiple layers are stacked and then tested again. That precision makes HBM more difficult to manufacture than conventional memory.

The payoff is much higher performance. Micron says its HBM4 uses a 2,048-pin interface running above 11 gigabits per second and delivers more than 2.8 terabytes per second of bandwidth per stack, more than twice the previous generation. The 12-high version holds 36 gigabytes, the same capacity as the comparable HBM3E stack, but moves data much faster. Micron also says HBM4 improves energy efficiency by 20% when comparing 12-high products at similar speeds.

The roadmap extends beyond HBM. DeBoer said Micron has sampled a 512-gigabyte DDR5 server module and plans a 1-terabyte version. The company targets a mid-20s percentage density improvement with its 1-delta DRAM node, while Gen11 NAND is designed to double the density of Gen9. Both technologies are scheduled to begin ramping in the second half of 2027.

For investors, greater wafer intensity cuts both ways. If AI systems keep demanding more HBM, a slower increase in bits per wafer can prolong tight supply and strengthen Micron's pricing power. At the same time, it can require more capital spending and introduces yield risk as products become more complex. Customers may also redesign systems or limit memory content if memory consumes too much of a server's bill of materials.

The webinar therefore supports an industry capacity argument, not a guaranteed earnings outcome or stock-price target. Micron's execution will depend on production yields, customer qualification and how quickly new wafer capacity becomes productive. HBM4's specifications show why demand is growing; the manufacturing steps show why satisfying that demand is not simply a matter of producing more conventional DRAM.